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rev.1.00, aug.20. 2004, page 1 of 26 hn58x2502i hn58x2504i serial peripheral interface 2k eeprom (256-word 8-bit) 4k eeprom (512-word 8-bit) electrically erasable and progr ammable read only memory rej03c0061-0100 rev.1.00 aug.20.2004 description hn58x25xxx series is the serial peripheral interface (spi) eeprom (electrically erasable and programmable rom). it realizes high speed, low power consumption and a high level of reliability by employing advanced monos memory technology and cm os process and low voltage circuitry technology. it also has a 16-byte page programming f unction to make it?s write operation faster. note: renesas technology?s serial eeprom are author ized for using consumer applications such as cellular phones, camcorders, audio equipments. therefore, please contact renesas technology?s sales office before using industrial applications such as automotive systems, embedded controllers, and meters.
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 2 of 26 features ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? type no. internal organization operating voltage frequency package hn58x2502fpie 2-kbit (256
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 3 of 26 pin arrangement 8-pin sop/tssop (top view) 1 2 3 4 8 7 6 5 v cc hold c d s q w v ss pin description pin name function c serial clock d serial data input q serial data output s chip select w write protect hold hold v cc supply voltage v ss ground
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 4 of 26 block diagram high voltage generator memory array y-select & sense amp. serial-parallel converter address generator control logic y decoder x decoder v cc v ss s w c hold d q
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 5 of 26 absolute maximum ratings parameter symbol value unit supply voltage relative to v ss v cc ? + ? + ? + ? + ? + parameter symbol min typ max unit supply voltage v cc 1.8 ? ? + ? ? ? ? + ? +
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 6 of 26 dc characteristics parameter symbol min max unit test conditions input leakage current i li ? s , d, c, hold , w ) output leakage current i lo ? ? ? ? ? ? ? ? ? ?
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 7 of 26 ac characteristics test conditions input pules levels: ? ?
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 8 of 26 (ta = ? + parameter symbol alt min max unit notes clock frequency f c f sck ? s active setup time t slch t css1 90 ? s not active setup time t shch t css2 90 ? s deselect time t shsl t cs 90 ? s active hold time t chsh t csh 90 ? s not active hold time t chsl ? ? ? ? ? ? ? ? hold not active t hhch ? ? hold active t hlch ? ? hold active t chhl ? ? hold not active t chhh ? ? ? ? ? ? ? hold high to output low-z t hhqx t lz ? hold low to output high-z t hlqz t hz ? ? + %
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 9 of 26 (ta = ? + parameter symbol alt min max unit notes clock frequency f c f sck ? s active setup time t slch t css1 100 ? s not active setup time t shch t css2 100 ? s deselect time t shsl t cs 150 ? s active hold time t chsh t csh 100 ? s not active hold time t chsl ? ? ? ? ? ? ? ? hold not active t hhch ? ? hold active t hlch ? ? hold active t chhl ? ? hold not active t chhh ? ? ? ? ? ? ? hold high to output low-z t hhqx t lz ? hold low to output high-z t hlqz t hz ? ? + %
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 10 of 26 timing waveforms serial input timing s c t chsl t slch t chdx t clch t chcl t shch t chsh t shsl t dvch msb in lsb in d q high impedance hold timing t chhl s hold c d q t hlch t chhh t hlqz t hhqx t hhch
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 11 of 26 output timing s c d q lsb out addr lsb in t qlqh t qhql t shqz t ch t cl t clqv t clqx t clqv t clqx
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 12 of 26 pin function serial data output (q) this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (c). serial data input (d) this input signal is used to transfer data serially into the device. it r eceives instructions, addresses, and the data to be written. values are latched on the rising edge of serial clock (c). serial clock (c) this input signal provides the timing of the serial interface. instructions, a ddresses, or data present at serial data input (d) are latched on the rising edge of serial cl ock (c). data on serial data output (q) changes after the falling edge of serial clock (c). chip select ( s ) when this input signal is high, the device is deselected and serial data output (q) is at high impedance. unless an internal write cycle is in progress, the device will be in the st andby mode. driving chip select ( s ) low enables the device, placing it in the active power mode. after power-up, a falling edge on chip select ( s ) is required prior to the start of any instruction. hold ( hold ) the hold ( hold ) signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to start the hold condition, the device must be selected, with chip select ( s ) driven low. write protect ( w ) this input signal is used to protect the memory against write instructions. when write protect ( w ) is held low, write instructions (wrsr, write) are ignored. no action on this signal can interrupt a write cycle that has already started.
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 13 of 26 functional description status register the following figure shows the status register format. the status register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. status register format 1 1 1 1 bp1 bp0 wel wip block protect bits write enable latch bits write in progress bits b0 b7 wip bit he write in progress wip bit inicates hether the eor is bs ith a write or write tats egister ccle wel bit he write enable latch wel bit inicates the stats o the internal write enable latch bp bp0 bits he block protect bp bp0 bits ar e nonolatile he eine the sie o the area to be rotecte against write instrctions instrctions each instrction starts ith a singlebte coe as sarie in the olloing table i an inali instrction is sent one not containe in the olloing table the eice atoaticall eselects itsel instrction et instruction description instruction format wren write enable 0000
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 14 of 26 write enable (wren): the write enable latch (wel) bit must be set prior to each write and wrsr instruction. the only way to do this is to send a write enable instruction to the device. as shown in the following figure, to send this instruction to the device, chip select ( s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits for the device to be deselected, by chip select ( s ) being driven high. write enable (wren) sequence s w c d q instruction 0123456 high-z v ih v il v ih v il v ih v il v ih v il 7
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 15 of 26 write disable (wrdi): one way of resetting the write enable latch (wel) bit is to send a write disable instruction to the device. as shown in the following figure, to send this instruction to the device, chip select ( s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits fo r the device to be desel ected, by chip select ( s ) being driven high. the write enable latch (wel) bit, in fact, becomes reset by any of the following events: ? ? ? ? ? w ) is driven low write disable (wrdi) sequence s w c d q instruction 1 0 234567 high-z v ih v il v ih v il v ih v il v ih v il
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 16 of 26 read status register(rdsr): the read status register (rdsr) inst ruction allows the status register to be read. the status register may be read at any time, even while a wr ite or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register continuously, as shown in the following figure. read status register (rdsr) sequence s w c d q status register out 01234567 0 1 2 3 4 5 6 77 8 9 10 11 12 13 14 15 high-z v ih v il v ih v il v ih v il v ih v il the status and control its o th e status register are as ollows wip it the write in progress (wip) it indicates whether the memory is usy with a write or write status register cycle. when set to 1 such a cycle is in progr ess. when reset to 0 no such cycles are in progress. wel it the write enale latch (wel) it indicates the status o the internal write enale latch. when set to 1 the internal write enale latch is set. when set to 0 the internal write enale latch is reset and no write or write status register instructions are accepted. bp1 bp0 its the bloc protect (bp1 bp0) its ar e non-volatile. they deine the sie o the area to e sotware protected against write instructions. these its are written with the write status register (wrsr) instruction. when one or oth o the bloc protect (bp1 bp0) its are set to 1 the relevant memory area (as deined in the status register ormat tale) ecome s protected against write (write) instructions. the bloc protect (bp1 bp0) its can e written provided that the hardware protected mode has not een set.
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 17 of 26 write status register (wrsr): the write status register (wrsr) instruction allows new values to be written to the status register. before it can be accepted, a write enable (wren) instruction mu st previously have been executed. after the write enable (wren) instruction has been decoded and execu ted, the device sets the write enable latch(wel). the instruction sequence is shown in the following figure. the write status register (wrsr) instruction has no effect on b6, b5, b4, b1 and b0 of the status register. b6, b5 and b4 are always read as 0. chip select ( s ) must be driven high after the rising edge of serial clock (c) that latches in the eighth bit of the data byte, and before the next rising edge of serial clock (c). othe rwise, the write status register (wrsr) instruction is not executed. as soon as chip select ( s ) is driven high, the self-timed write status register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status register cy cle, and is 0 when it is completed. when the cycle is completed, write enable latch(wel) is reset. the write status register (wrsr) instruction allows the user to change the values of the block protect (bp1, bp0) bits, to define the size of the area that is to be treated as read-only, as defined in the status register format table. the contents of block protect (bp1, bp 0) bits are frozen at their current va lues just before the start of the execution of the write status register (wrsr) instruction. the new, updated values take effect at the moment of completion of the execution of write status register (wrsr) instruction. write status register (wrsr) sequence s w c d q status register in msb 01234567 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 high-z v ih v il v ih v il v ih v il v ih v il
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 18 of 26 read from memory array (read): as shown in the following figure, to send this instruction to the device, chip select ( s ) is first driven low. the bits of the instruction byte and the address bytes are then shifted in, on serial data input (d). the addresses are loaded into an internal address register, and the byte of data at that address is shifted out, on serial data output (q). the most significant address (a8) should be sent as fifth bit in the instruction byte. if chip select ( s ) continues to be driven low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. when the highest address is reached, the address counter rolls over to zero, allowing the read cycle to be continued indefinitely. the whole memory can, therefore, be read with a single read instruction. the read cycle is terminated by driving chip select ( s ) high. the rising edge of the chip select ( s ) signal can occur at any time during the cycle. the addressed first by te can be any byte within any page. the instruction is not accepted, and is not executed, if a write cycle is currently in progress. read from memory array (read) sequence s w c d q 8-bit address data out 2 data out 1 01234567 a0 a1 a2 a3 a5 a6 a7 a8 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 high-z v ih v il v ih v il v ih v il v ih v il 0 1 2 3 4 5 6 77 instruction note 1. depending on the memory sie as shown in t he ollowing tale the most signiicant address its are dont care. address range bits device hn58x2504i hn58x2502i address bits a8 to a0 a7 to a0 note: 1. a8 is don?t care on the hn58x2402.
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 19 of 26 write to memory array (write): as shown in the following figure, to send this instruction to the device, chip select ( s ) is first driven low. the bits of the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (d). the instruction is terminated by driving chip select ( s ) high at a byte boundary of the input data. in the case of the following figure, this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. the self-timed write cycle starts, and continues for a period t wc (as specified in ac characteristics). at the end of the cycle, the write in progress (wip) bit is reset to 0. if, though, chip select ( s ) continues to be driven low, as shown in the following figure, the next byte of the input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal write cycle. each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. if the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data th ere are overwritten with the incoming data. (the page size of these device is 32 bytes). the instruction is not accepted, and is not executed, under the following conditions: ? ? ? ? w ) is low
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 20 of 26 byte write (write) sequence (1 byte) s w c d q 8-bit address data byte 1 01234567 0 1 2 3 a5 a6 a7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 high-z v ih v il v ih v il v ih v il v ih v il 4 5 6 7 a0 a1 a2 a3 instruction a8 note 1. depending on the memory sie as shown in address range bits tale the most signiicant address it is dont care.
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 21 of 26 byte write (write) sequence (page) s w c d q 8-bit address data byte 1 01234567 0 1 2 3 a5 a6 a7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 high-z v ih v il v ih v il v ih v il v ih v il 4 5 6 7 a0 a1 a2 a3 instruction s w c d q data byte 3 data byte n 24 25 26 27 28 29 30 31 7 32 33 34 35 36 37 38 39 high-z v ih v il v ih v il v ih v il 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 data byte 2 a8 note 1. depending on the memory sie as shown in address range bits tale the most signiicant address it is dont care.
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 22 of 26 data protect the block protect bits (bp1, bp0) define the area of me mory that is protected ag ainst the execution of write cycle, as summarized in the following table. when write protect ( w ) is driven low, write to memory array (write) and write status register (wrsr) are disabled, and wel bit is reset. write protected block size status register bits array addresses protected bp1 bp0 protected blocks hn58x2504i hn58x2502i 0 0 none none none 0 1 upper quarter 180h ? ? ? ? ? ?
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 23 of 26 hold condition the hold ( hold ) signal is used to pause any serial communi cations with the device without resetting the clocking sequence. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to enter the hold condition, the device mu st be selected, with chip select ( s ) low. normally, the device is kept select ed, for the whole duration of the hold condition. deselecting the device while it is in the hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. the hold condition starts when the hold ( hold ) signal is driven low at the same time as serial clock (c) already being low (as shown in the following figure). the hold condition ends when the hold ( hold ) signal is driven high at the same time as serial clock (c) already being low. the following figure also shows what happens if the rising and falling edges are not timed to coincide with serial clock (c) being low. hold condition activation c hold hold status hold status
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 24 of 26 notes data protection at v cc on/off when v cc is turned on or off, noise on s inputs generated by external circuits (cpu, etc) may act as a trigger and turn the eeprom to unintentional program mode. to prevent this unintentional programming, this eeprom have a power on reset function. be careful of the notices described below in order for the power on reset function to operate correctly. ? s should be fixed to v cc during v cc on/off. low to high or high to low transition during v cc on/off may cause the trigger for the unintentional programming. ? ? ? ?
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 25 of 26 package dimensions hn58x2502fpie/hn58x2504fpie (fp-8dbv) package code jedec jeita mass (reference value) fp-8dbv ? ? 0.08 g *pd plating 0 ? ? 8 ? 1.27 8 5 14 0.10 0.25 m 1.73 max 3.90 *0.20 0.05 4.89 0.14 + 0.114 ? 0.038 0.69 max 6.02 0.18 0.60 + 0.289 ? 0.194 1.06 5.15 max *0.40 0.05 unit: mm
hn58x2502i/hn58x2504i rev.1.00, aug.20. 2004, page 26 of 26 hn58x2502tie/HN58X2504TIE (ttp-8dav) 0.50 0.10 0? ? 8? *0.15 0.05 6.40 0.20 0.10 1.10 max 0.13 m 0.65 14 85 4.40 3.00 3.30 max 0.805 max *0.20 0.05 0.07 +0.03 ?0.04 1.00 package code jedec jeita mass (reference value) ttp-8dav ? ? 0.034 g *pd plating unit: mm
revision history hn58x2502i/hn58x2504i data sheet contents of modification rev. date page description 0.01 jul. 29, 2003 ? initial issue 1.00 aug.20.2004 ? ? 2 25-26 deletion of preliminary deletion of package: son (tnp-8da) ordering information deletion of hn58x2502f pi, hn58x2504fpi, hn58x2502ti, hn58x2504ti addition of hn58x2502fpi e, hn58x2504fpie, hn58x2502tie, HN58X2504TIE package dimensions: change of dimensions fp-8db to fp-8dbv ttp-8d to ttp-8dav
keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is a lways the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placeme nt of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies o r errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas techn ology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materi als. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500 fax: <1> (408) 382-7501 renesas technology europe limited. dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585 100, fax: <44> (1628) 585 900 renesas technology europe gmbh dornacher str. 3, d-85622 feldkirchen, germany tel: <49> (89) 380 70 0, fax: <49> (89) 929 30 11 renesas technology hong kong ltd. 7/f., north tower, world finance centre, harbour city, canton road, hong kong tel: <852> 2265-6688, fax: <852> 2375-6836 renesas technology taiwan co., ltd. fl 10, #99, fu-hsing n. rd., taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. 26/f., ruijin building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1, harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices ? 2004. renesas technology corp., all rights reserved. printed in japan. colophon .1.0

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